Sub‐20 nm Ferroelectric Junctionless Gate‐All‐Around Metal‐Oxide‐Semiconductor Field‐Effect Transistor for Low‐Power Applications: Switching Performances and Subthreshold Circuit Analysis

Abstract

Single‐gate metal‐oxide‐semiconductor field‐effect transistors (MOSFET) suffer from several basic physical and electrical limitations for further scaling in deep nanoscale domains, which are often known as short‐channel and reliability effects. The junctionless (JL) gate‐all‐around (GAA) MOSFET design is claimed to provide superior performance and scalability properties as well as reduced elaboration cost in comparison to that of double‐gate and Fin‐FETs. However, further improvements regarding the subthreshold slope (SS) and power consumption should be carried out to better minimize the problem of commutation speed and power dissipation of the nanoscale device. In this context, this work aims at investigating the performance of ferroelectric (FE) JLGAA MOSFET including the impact of the FE material variability on the subthreshold performances, such as subthreshold slope and threshold voltage ( V th ). In this framework, the transistor subthreshold properties will be analytically modeled, where accurate models of subthreshold current, SS and V th will also be derived and validated by technology computer‐aided design (TCAD)‐based numerical simulations. The investigated device is implemented to investigate the performance of a nanoelectronic inverter gate in the subthreshold regime. The proposed investigation can open new paths for developing efficient field effect transistor (FET)‐based low‐power nanoelectronic digital circuits.