Performance evaluation and enhancement of high-voltage direct current circuit breakers integrated with superconducting fault current limiters

Abstract

<title>Abstract</title> Arc interruption within high-voltage direct current (HVDC) circuit breakers (CBs) presents a significant challenge for the stability and operation of HVDC grids. To facilitate the investigation of arc interruption phenomena in HVDC-CBs, black box arc models are utilized. Particularly, those employing the Cassie and Mayr dynamic arc equations to characterize the nonlinear arc conductance. The primary objective of this study is to analyze the influence of varying black box arc parameters. Specifically, cooling power factor, arcing time constant, commutation capacitance, and commutation inductance on the arcing duration. This analysis will be conducted in the absence and presence of diverse superconductor fault current limiter (SFCL) configurations, with the ultimate goal of identifying optimal arcing duration values. In this paper, MATLAB simulations for a 450 km HVDC transmission line are used to find the optimal arcing time by comparing various simulation conditions. This is accomplished by proposing the introduction of a resistive, capacitive, and inductive SFCL connected in series with the original Cassie and Mayr arc models.