High Throughput Implementation of AES Algorithm Using Radiation Tolerant FPGA for Secure LST-SW Algorithm

Abstract

Advanced Encryption Algorithms have become a solution for securing data in different fields. In a hardware implementation, we can achieve more flexibility and performance compared to the software implementation which is more vulnerable to outside attacks. This paper describes a secure implementation of the LST-SW algorithm which is one of the important parameters computed by the earth observation satellite. The AES algorithm is implemented using a pipelined architecture in order to increase the throughput of the algorithm. The implementation has been successfully done by radiation-hardened Virtex-4QV XQR4VSX55 FPGAs using Xilinx ISE 14.7. The hardware results of the proposed design show that this implementation can achieve a throughput of 1989.97 Mbps and take 14 % of the slice in area utilization with 7 blocks of RAM. Compared to the previous works, this implementation improves the metric of the throughput and achieves the best trade-off between the resource consumption since we have used pipelined architecture which takes more resources.