FPGA-Based Real-Time Implementation of a Multi-Staged Hyperchaotic Image Encryption Algorithm

Abstract

With the growing demand for secure and efficient image transmission, hardware-based encryption solutions are gaining increased attention. This paper presents a secure, multi-staged image encryption algorithm and its real-time implementation on FPGA hardware. The algorithm begins with an XOR-based diffusion using a key derived from a 10D hyperchaotic system, followed by substitution via an S-box generated from the same system. Next, the Arnold Cat Map scrambles pixel positions, after which a second diffusion is applied using a key from a 5D memristor-based hyperchaotic system, along with a second S-box. The design ensures strong key sensitivity and high resistance to statistical, differential, and brute-force attacks. Hardware implementation on an FPGA platform demonstrates the algorithm’s practicality and efficiency for real-time image encryption applications.