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Disaster recognition is critical for emergency response, enabling rapid identification of hazards such as fires, floods, and building collapses through automated image analysis. Deep convolutional neural networks (CNNs), such as ResNet-18, achieve high classification accuracy but are computationally demanding, limiting their deployment on resource-constrained platforms. While GPUs provide parallel processing, their high power consumption hinders onboard application. Field Programmable Gate Arrays (FPGAs) offer a compelling alternative, combining customizable hardware with superior energy efficiency for real-time inference. In this work, we deploy a ResNet-18 model trained on the AIDER dataset, which contains 8,640 images across five disaster-related classes, on a Xilinx Zynq UltraScale+ MPSoC (ZCU104) using the Vitis-AI development flow. Our FPGA implementation achieves 96.96% accuracy, with an inference latency of 5.89 ms per frame and a throughput of 169 FPS. Compared to a CPU baseline (29.3 ms latency, 34 FPS), this corresponds to a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.9 \times$</tex> latency reduction, a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5 \times$</tex> throughput improvement, and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$14.9 \times$</tex> energy-efficiency gain (FPS/W). These results show that FPGA-based acceleration can provide high-performance, energy-efficient, and real-time disaster recognition. This shows how useful it can be for autonomous aerial systems and onboard computing applications.
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DOI: 10.1109/icm66518.2025.11322530
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