Ferroelectric Tunnel FET

Abstract

After identification and experimental verification of the negative capacitance (NC) in ferroelectric material, significant research efforts have been continued with classical FET structures like bulk MOSFET, FinFET, gate all around(GAA) and nanosheet FET for/achieving improvement of device figures of merits(FoMs) such as I ON , I OFF , I ON /I OFF subthreshold swing(SS) for various applications. Low power use has become a serious issue for semiconductor players. Due to the large values of subthreshold swing (>60 mV/decade) conventional FETs structures such as bulk MOSFET, FinFET, gate all around (GAA), and nanosheet FET have failed to fulfill the requirements of ultra-low power uses. The scientific field behind classical MOS structures has not allowed the use of <0.5 V power supply. The tunnel FET was found to be the most suitable FET device, followed by band-to-band tunnel tunneling(BTBT) for ultra-low power uses owing to its smaller values of SS <60 mV/ decade. However, a low on-current (I ON ) limitation forces more scientific exercise to achieve improved circuit design parameters with tunnel FET, such as I ON , I OFF , I ON /I OFF , and SS. The ferroelectric material was found to be suitable for reducing the applied power supply (V DD ). In this chapter, the authors focused on investigating the impact of ferroelectric gate materials in conventional tunnel FET. We used a double-gate tunnel FET (DG-TFET) structure. In conventional DGTFET structures, composite gate material engineering has been implemented with the help of a ferroelectric material and HFO 2 . The negative capacitance (NC) in ferroelectric materials enables internal voltage amplification inside device, potentially reduce power (V DD ) without any compromise the devices figure of merits(FoMs) such as I ON , I OFF and I ON /I OFF ratio. The obtained results show a low I OFF (~10 −20 A /μm) and I ON (~10 −5 A /μm), while the SS was also reduced significantly.