DC-DC Converter Optimization Strategies for Improved Performance with Resistive Loads in Low-Power Applications

Abstract

This study explores the performance characteristics of six distinct DC-DC boost converter configurations, each optimized to achieve a voltage gain of 2. The configurations analyzed include Series/Parallel, 3-clock Fibonacci, Ladder <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C=10 \mu\mathrm{F})$</tex>, Doubler <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C=10 \mu\mathrm{F})$</tex>, Ladder <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C =500 \mu\mathrm{F})$</tex>, and Doubler <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C=500 \mu\mathrm{F})$</tex>. Each configuration is evaluated based on parameters such as efficiency, optimum resistive load range, settling time, and output DC ripple. The findings indicate that the Series/Parallel configuration offers the highest efficiency at 94.53%, while the Ladder configuration using <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$500 \mu\mathrm{F}$</tex> capacitance achieves a notable efficiency of 97.24% despite a longer settling time. These results underscore the trade-offs inherent in designing DC-DC converters for a range of applications, highlighting the need for careful consideration of performance metrics based on specific operational requirements.