CONFIGURABLE NAIVE BAYES IMPLEMENTATION ON FPGA USING PARTIAL RECONFIGURATION

Abstract

The Naive Bayes classifier is a fundamental algorithm in machine learning, known for its simplicity and effectiveness in various predictive modeling scenarios. However, its deployment in real-time applications demands efficient hardware implementations that can adapt dynamically to varying computational needs and model specifications. This work presents a novel FPGA-based implementation of Naive Bayes classifiers that leverages partial reconfiguration to enhance flexibility and resource efficiency. Our method employs a modular architecture that allows seamless switching among various Naive Bayes models, such as Gaussian, Multinomial, and Bernoulli, enhancing system flexibility without halting ongoing processes. By utilizing partial reconfiguration, our implementation minimizes the FPGA resource utilization, enabling more efficient use of hardware. We thoroughly evaluate our system, focusing on reconfiguration time and resource efficiency. We demonstrate that our approach provides the operational flexibility needed for real-time data processing tasks, enabling quick adaptation to variable data types and distributions without interrupting ongoing processes. This adaptive framework supports dynamic scenarios, facilitating immediate updates in response to evolving conditions with minimal downtime.