CMOS Compatible Cost-Effective eGaN HEMT Using B-Doped Schottky Barrier Gate on Compliant SOI Substrates

Abstract

This paper introduces a cost-effective CMOS-compatible enhanced mode GaN-on-SOI HEMT comparable to IMEC's platform. Notably, we employed a Boron-doped p-gate instead of Magnesium doping where BN discs are readily available as dopant source in CMOS technology. Furthermore, our SOI structure integrates a Si (100) active layer in lieu of Si (111) on a Si (100) substrate separated by buried oxide. This allows to use Si (100) SIMOX SOI wafers instead of wafer bonding and grinding of two oxidized Si (111) and Si (100) wafers. These modifications result in more CMOS-compatible cost-effective technology. The simulation results exhibit a close correspondence to IMEC's platform, revealing a threshold voltage of approximately 1.8 V, a low leakage current of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1}\times \mathbf{10}^{-\mathbf{10}}$</tex> A and a maximum drain current of 6 A at Vgs = 6 V for a 36 mm effective transistor width.