Battery‐free ultra‐low‐power radio‐frequency receiver for mm‐wave applications using 130‐nm CMOS technology with harvested DC supplies

Abstract

Summary This paper presents a battery‐free ultra‐low‐power (ULP), highly integrated, and wide‐bandwidth low‐IF radio‐frequency (RF) receiver designed for millimeter‐wave (mm‐Wave) applications, utilizing 130‐nm CMOS technology. The suggested RF receiver is suitable for K‐band (n258) at 26 GHz, Ka‐band (n261 and n257) at 28 GHz, and the LMDS band at 28 GHz in fifth‐generation applications. The proposed radio receiver consists of a low‐noise driver stage implemented using a complementary current‐reuse common gate with an active shunt feedback configuration and an in‐phase/quadrature‐phase (I/Q) demodulator. The proposed RF receiver employs transformer coupling to isolate the DC path between the transconductance stage (RF stage) and the switching stage (IF stage). The driver stage expands the RF input impedance while maintaining acceptable linearity and gain with ultra‐low DC power dissipation. The DC supplies for the proposed mm‐Wave RF receiver are generated using two novel energy‐harvesting voltage doubler circuits to provide positive and negative voltages. The proposed mm‐Wave radio receiver consumes 0.475 mW from a 1.1 V DC supply and exhibits a power conversion gain (CG) of 6.3 dB, with a 3 dB frequency bandwidth extending from 22 to 32 GHz. The input 1‐dB compression point (P1dB) of the RF receiver is −2.65 dBm, and the input third‐order intercept point (IIP3) is 7.35 dBm. With a sensitivity of −66.5 dBm at a 100 MHz channel bandwidth and a dynamic range of 63.85 dB, the suggested receiver demonstrates notable performance characteristics. The proposed radio receiver boasts an excellent figure of merit (FoM) at 215 dB, surpassing published works by a margin of 8–31 dB. The primary positive supply voltage is derived from a double‐band positive voltage doubler with series resonance feedback and parallel resonance networks, efficiently achieving the desired DC voltage and output current (1.1 V and 450 μA). Meanwhile, the negative gate bias is provided by a negative voltage doubler, ensuring the necessary negative voltage (−0.5 V) without any current conditions.