A High-Resolution Non-Volatile Floating Gate Transistor Memory Cell for On-Chip Learning in Analog Artificial Neural Networks

Abstract

This paper proposes a high-resolution non-volatile memory cell design that addresses the most substantial limitations associated with the effective implementation of analog long-term memory storage solution. Prior research efforts often suffer from limited resolution, hindering their ability to accurately represent fine-grained weight adjustments required for effective learning in analog neuromorphic systems. This work effort has been channeled toward crafting conductive circuit designs using 90 nm complementary metal-oxide semiconductor technology for on-chip learning applications in analog neuromorphic systems. The operational mechanism of the cell involves the storage of charge on the floating gate of the NM0 transistor. The writing process is accomplished through hot-electron injection, while the erasure of stored information is executed via gate oxide tunneling. An advantageous feature of this cell is its capability to facilitate simultaneous reading and writing of data. The reduction of errors that may arise due to oxide mismatch or charge trapping is achieved through feedback control incorporation during the writing phase. The memory reveals clear synaptic behavior characteristics in storing and retrieving analog information reliably including, good memory cell resolution, good charge retention rate, reliable operation in noisy environments, and high resolution with faster learning with a power consumption of 1.06 µW and an output current of 10 µA under a typical operating voltage of 1 V. This strategic implementation enhances precise and reliable weight updates within neuromorphic analog artificial neural networks, which is essential for ensuring accurate on-chip learning outcomes as well as minimizing power consumption.