A Design Aid Tool for Asynchronous SAR ADCs

Abstract

Successive approximation register analog-to-digital converters (SAR ADCs) are one of the most common ADC architectures due to their high energy efficiency in the medium-to-high resolution range. Consequently, they are essential for many applications, including the Internet of Things. However, the design process for SAR ADCs can be time-consuming and error-prone. Assessing the feasibility of specific process node requirements promptly, especially when considering complex specifications and tradeoffs, poses a significant challenge. This work presents a design automation tool for asynchronous SAR ADCs. The tool takes top-level specifications as input and provides device sizing results. The automation process adopts a hybrid approach, combining equations and lookup tables (LUTs) to automate critical design steps. These steps include capacitor sizing, sample and hold sizing, and comparator design. Both design time and manual effort are substantially reduced when employing this tool. To showcase the efficacy of the proposed tool, an 8-bit 8MS/s ADC design was generated in 65-nm CMOS technology. The resulting ADC performs very well, with an output power consumption of 36.78 μW at a supply voltage of 1 volts, a FoMw of 18.69 fJ/conversion-step, and a FoMs of 159.94 dB.