A Comparative Study of Hardware Accelerators for Autonomous Vehicles in Recent ADAS Practices

Abstract

This review provides an overview of hardware accelerators in Autonomous Vehicles (AVs), specifically within Advanced Driver Assistance Systems (ADAS). It examines various accelerators, including CPUs, GPUs, FPGAs, and ASICs, highlighting their roles in key ADAS functions such as object detection, lane detection, traffic sign recognition, and pedestrian detection. The paper also reviews key detection algorithms, including one-stage models such as YOLO and SSD, as well as two-stage architectures such as R-CNN-based detectors, highlighting their deployment requirements across different hardware platforms. Particular attention is given to the trade-offs among computational performance, latency, energy efficiency, flexibility, cost, integration complexity, cybersecurity, and automotive reliability. The review shows that while CPUs remain essential for general control and system management, specialized accelerators are increasingly required to meet the real-time constraints of ADAS and autonomous driving applications. Overall, this study provides researchers, developers, and automotive engineers with practical insights for selecting suitable hardware accelerators for efficient, reliable, secure, and scalable autonomous vehicle systems.